>>117 (cont.)
I've not been able to achieve too much over the elapsed time, being fairly scatter-brained (I've even been reading Seneca of all people!), but I did reread a few of your articles, of which I have meaningful comments or questions on two. I'm not sure if it would be more appropriate to send these via the comment system perhaps without some of my funny thoughts so that others could avoid asking the same questions.
Do you consider bit-parallelism an insidious optimization in the same fashion as byte-addressable memory and registers (all together a tyranny of the machine word)? My thinking is the register follows naturally from operations on word-sized units, and much less so byte-addressable memory from byte multiple word sizes. Bit-parallelism stands out of place in a system without these two insidious optimizations to me.
If bit-parallelism be an insidious optimization do you know a way to reconcile bit-serial operation with a high-level architecture? Bit-serial operation typically imply many computers which makes complex operations more costly (although with my limited knowledge garbage collection and type checking would still be sufficiently cheap). A heterogeneous architecture or something like a central executive for these functions would harm the design in my view. This is all without considering that a great deal of complexity is also introduced in having many computers.
I had a funny thought of memory spitting instructions and data together directly to the computers with each instruction being a one-to-one memory transformation such that explicit addresses and memory management more generally could be removed (the idea of removing control-flow made me think of APL, and of removing addresses in this way in turn). I didn't work it out any further however, and it's likely a common delusion; even still were there a way to hide or remove memory management entirely to me this would make a computer more elegant (metaprogramming to reduce constants as you seek to advance in Meta-CHIP-8 would be negatively impacted). (A sort of stack machine with a single stack taking up all of memory (a memory-to-memory stack-machine) could be thought of as just combinators and other functions in RPL, that is operand rather than memory management, but it still doesn't feel quite perfect.)
I've understood most the faults and features of Meta-CHIP-8 well enough; amusingly the populating of data for meta-programming and naming reminded me of the Harvard Architecture. I am confused however by the use of the three-bit association in the hextet for the instructions ExxCxx through ExxFxx; likely related, I don't understand the meaning of "routine information" and "routine entry" in the definitions of instructions ExxExx and ExxFxx. Also what does "instate" in the definition of the MMC hook FE5 mean?
This will be the first I try to rederive myself, but I don't have a time schedule currently, and as I mentioned I've not been very productive lately.